My name is Trevor Hendricks. I am a senior and I am getting an electrical engineering major and a computer engineering minor at Montana State University. My primary focus for this project is on the vhdl for the event detector logic as well as doing the interface logic between the UART and event detector.
The event detector must be able to read in pulses as short as 5 nanoseconds. To perform this every sensor input channel will have four flip flops connected together to make a shift register. These flip flops will run at 400 MHz giving them a clock period of 2.5 nanoseconds. The shift registers will act as a serial to parallel converter turning the high speed input into a 100MHz parallel output. This output is then stored into a block ram whose address is controlled by a counter. The contents of the block ram are then read by a state machine that passes them in 8 bit packets to the UART to be sent out. For testing purposes the system does not run continuously because of data constraints placed by having to send all recorded data over serial. Instead the state machine is set to receive an enable signal from the UART which starts an acquisition process where the system will record for 40 nanoseconds and then continuously broadcast out the recorded data until a new acquisition signal is received which restarts the process.